FIG. 1 shows a schematic diagram of a typical phase lock loop (PLL) circuit employing a charge pump. A typical PLL circuit 100 consists of a phase frequency detector (PFD) 104 which detects a phase error, via a phase comparison, between a reference clock signal, denoted as REF_CLK, and a divided output clock from a divide-by-N divider 124. The PFD 104 generates and outputs UP and DOWN signals which drive a charge pump 106. The charge pump 106 injects a charge proportional to the detected phase error into a loop filter 116. The loop filter 116 then generates a control voltage Vctrl (or current) that is an input to a voltage (or current) controlled oscillator (VCO) 122. The VCO 122 generates a VCO output signal, denoted as VCO_CLK, whose frequency is proportional to the control voltage Vctrl. It should be noted that the PFD 104 is clocked by the reference clock signal REF_CLK; i.e. the phase comparisons occur at the reference frequency interval.
The reference clock signal REF_CLK is a function of a clock signal from an external reference oscillator (not shown) and may be a fraction of the external reference oscillator, the fraction being derived by a divider (not shown) in a path between the external reference oscillator and the PFD 104.
In a locked condition, the UP and DOWN pulses are of substantially equal duration and no net charge is injected into the loop filter 116. Hence the control voltage Vctrl (or current) is ideally at a constant value which ensures that the VCO output signal VCO_CLK is at a constant frequency. The loop filter 116 typically accumulates a charge to produce a filtered control voltage that adjusts the VCO 122 output frequency.
The loop filter 116 is shown to include a first order loop filter implementation that comprises a series combination of a resistor (RFILT) 118 and a capacitor (CFILT) 120 in parallel with the charge pump 106 output. The loop filter 116 is only exemplary and may also include other components. For example, commonly an extra pole capacitor (not shown) is placed in parallel with the charge pump 106 output. The extra pole capacitor may be 1/10 the value of capacitor 120. The extra pole capacitor does not affect PLL 100 settling time or loop stability, but improves reference spur rejection in the VCO 122 output signal.
The charge pump 106 includes current sources 108 and 114 and switches 110 and 112. The switch 110 when closed passes the UP pulse to the loop filter 116. The switch 112 passes the DOWN pulse to the loop filter 116 when closed. The output of the PFD 104 controls the charge pump 106 so as to increase or decrease the control voltage Vctrl (or current) to the VCO 122 input.
FIG. 2 shows a set of waveforms 200 for a reference clock signal REF_CLK, a VCO output signal VCO_CLK, UP and DOWN pulses, and a control voltage Vctrl “ripple” associated with the PLL circuit 100 of FIG. 1. The waveform of the control voltage Vctrl illustrates a voltage droop due to the charge pump leakage in an OFF state. The voltage droop corresponds to a sloped (decreasing) waveform of the control voltage Vctrl which begins after a falling transition of the UP or DOWN pulses and continues to droop until a beginning of the next REF_CLK rising edge or beginning of a rising transition of the UP pulse. The waveform of the control voltage Vctrl is measured at a node Vctrl of the loop filter 116. In order to compensate for the voltage droop, the UP pulse is extended to compensate for the charge lost due to the leakage. The extended portion of the UP pulse is shown hatched in the waveform. Thus, the control voltage Vctrl gradually increases until the rising transition of the DOWN pulse. During the interval of the DOWN pulse, the control voltage Vctrl remains substantially at a constant level. The waveform of the VCO output signal VCO_CLK represents the modulation of the output frequency (VCO output signal) of the VCO 122 due to the voltage droop or voltage ripple on the control voltage Vctrl. During a lock condition, the control voltage Vctrl is ideally a constant or DC voltage. Any periodic deviation from this DC or average value is said to be a ripple.
In current nanometer processes, the leakage current of a transistor in the “off” state can be quite significant. The charge pump 106 within PLL 100 is typically implemented using transistor based current sources that are turned on for the duration of the UP or DOWN pulses and are turned off otherwise. However the leakage current of these transistors in the OFF state can significantly alter the charge accumulated onto the loop filter 116. The PLL circuit 100 has to ensure that the locked condition is maintained by compensating for this charge loss due to leakage. The compensation is accomplished by the injection of an equal and opposite amount of extra charge at the beginning of each phase comparison. The leakage current charge loss and compensation charge introduces voltage “ripple” on the control voltage Vctrl to the voltage controlled oscillator (VCO) which manifests as deterministic jitter in the time domain or reference spurs in the frequency domain on the VCO output signal VCO_CLK of the VCO 122. Both effects can be undesirable depending on the target application. The undesirable effects are further exacerbated in low voltage designs that typically use high voltage or current gain VCO architectures to maximize the tuning range (i.e. to generate a wide range of frequencies from a limited control voltage or current range).
In one solution to lower the leakage current, thick-oxide transistors are employed in the charge pump. However, the option of using thick-oxide transistors may not be available in a particular integrated circuit process technology or may require the use of costly extra mask process steps. In another solution, a large loop capacitance is used to minimize voltage change for a given leakage current which results in an integrated circuit area and cost penalty.
There is therefore a need to mitigate charge pump leakage current without the expense of thick oxide transistors or a large loop capacitor on-chip.
There is also a need for a circuit that reduces the effect of a charge pump leakage in a phase lock loop with the minimum integrated circuit cost and area penalty.